1. Field of the Invention
The present invention relates to a distortion compensation apparatus to compensate for distortion occurring in an amplifier, and more particularly to a distortion compensation apparatus for realizing distortion compensation of high precision, by adjusting the timing for controlling the amount of distortion generated on a signal to be provided for the amplifier.
2. Description of the Related Art
For example, in a mobile wireless communication system such as cellular phone system, in order to assure wireless communication with a mobile station existing at an end of an area (cell) covered by a base station, and in order to realize wireless transmission of signals simultaneously to plural mobile stations (plural users) from the base station depending on the status of communication, the base station is required to send signals with a large power. Similarly, in a repeater station (repeating amplifier) for receiving wireless transmitted signals from the base station, amplifying these signals, and sending the amplified signals to mobile stations by wireless transmission, it is also required to send signals with a large power.
Accordingly, in such a base station or a repeater station, signals to be transmitted (for example, modulated waves) are amplified to a desired level by means of a (large) power amplifier (PA) capable of covering a physical distance up to the end of the cell. In such an amplifier, however, a nonlinear response (AM-AM conversion or AM-PM conversion) characteristic may take place near the critical point (saturation point) of an element, and nonlinear distortion may occur.
Radio Law demands wireless communication service providers to strictly regulate their band limit in order to eliminate effects between different services of wireless communication offered by using adjacent bands.
As a method of compensating for nonlinear distortion occurring in the amplifier, hitherto, it was proposed to use a predistorter type compensation system to compensate for the nonlinear distortion by generating distortion having a reverse characteristic to the nonlinear distortion occurring in the amplifier (that is, the distortion to cancel the nonlinear distortion) in a prior stage.
Other methods of compensating for nonlinear distortion include, for example, a feed-forward type distortion compensation system and negative feedback type distortion compensation system. In the feed-forward type distortion compensation system, the operation is advantageously stable, but it is required to extract a distortion component (occurring in the main amplifier) in the distortion detecting loop, and to amplify the distortion component with a sub amplifier in the distortion compensation loop and subtract the amplified signal from the output signal of the main amplifier. Hence, there are problems in that the circuit is complicated, and the power source efficiency is lowered by the sub amplifier. In contrast, in the predistorter type distortion compensation system, the structure is relatively simple, and a sub amplifier is not needed, and it is, hence, advantageous in both circuit scale and power source efficiency.
An example of a (distortion compensation) amplifying device having a predistorter for compensating for distortion by such a predistorter type distortion compensation system is explained below.
FIG. 11 shows an example of circuitry of an amplifying device with a predistorter (amplifier with predistortion function), and the operation of this amplifying device is explained below by referring to the diagram. This amplifying device is installed in the transmission section of a base station or repeater station, and the signal to be transmitted (transmission signal) is entered from a transmitter. This signal is amplified in the amplifier, and sent out to an antenna.
First, the signal to be transmitted which is issued from the transmitter is put into this predistortion circuit, and the signal is distributed into two, and one distribution signal is fed into delay means 81, and other distribution signal is fed into a level detector 85.
FIG. 12 shows an example of spectrum of a signal in an input stage from the transmitter to the amplifying device, in which the axis of abscissas denotes the signal frequency [kHz], and the axis of ordinates indicates the signal level by power ratio [dB]. As shown in the diagram, at this stage, there is no distortion by a predistorter (a variable attenuator 82 and a variable phase shifter 83) and no distortion by an amplifier 84, and hence the spectrum shows a low level of an unnecessary signal out of the band of use.
The delay means 81 delays the input signal (one distribution signal), and it sends it to the variable attenuator 82.
The variable attenuator 82 changes (attenuates) the amplitude of the signal entered from the delay means 81, depending on the (analog) control signal entered from a D/A converter 88, described below, to generate an amplitude distortion in an amount corresponding to the control signal to the input signal, and sends this signal (including amplitude distortion) to the variable phase shifter 83.
The variable phase shifter 83 changes the phase of the signal entered from the variable attenuator 82 depending on the (analog) control signal entered from a D/A converter 89, described below, to generate a phase distortion in an amount corresponding to the control signal to the input signal, and sends this signal (including phase distortion) to the amplifier 84.
In this example, the predistorter (predistortion generator) is composed of the variable attenuator 82 and variable phase shifter 83 connected in series and control systems 81, 85, to 90 for controlling them.
The amplifier 84 amplifies the input signal from the variable phase shifter 83 to a desired level, and sends out the amplified signal (from the amplifying device) to the antenna.
FIG. 13 shows an example of a spectrum of a signal issued from the amplifier 84 when the distortion is not compensated, in which the axis of abscissas denotes the signal frequency [kHz], and the axis of ordinates indicates the signal level by power ratio [dB]. As shown in the diagram, in this case, the spectrum shows there is a distortion component (leak power to adjacent channels) out of the band of use due to distortion occurring in the amplifier 84.
Such a distortion component can be compensated for by generating distortion of a reverse characteristic to the distortion occurring in the amplifier 84 (amplitude distortion or phase distortion) by the predistorter (variable attenuator 82 and variable phase shifter 83).
FIG. 14 shows an example of a spectrum of a signal issued from the amplifier 84 when the distortion is compensated for by the predistorter, in which the axis of abscissas denotes the signal frequency [kHz], and the axis of ordinates indicates the signal level by power ratio [dB]. As shown in the diagram, in this case, the spectrum shows a decrease of the distortion component (leak power to adjacent channels) out of the band of use occurring in the amplifier 84.
The level detector 85 is composed of, for example, an envelope detector for detecting the envelope of a signal, a low pass filter (LPF) for extracting a specific frequency component only about the detected envelope, and an A/D (analog/digital) converter for converting the detected envelope component from analog to digital signal. The level detector 85, having such a structure, detects the level (for example, power level) of the input signal (other distribution signal), and issues the result of detection to a controller 90 by a digital value.
Distortion extracting means 86 is composed of, for example, a directional coupler, and extracts distortion (for example, part of the amplified signal) included in the amplified signal issued from the amplifier 84, and sends out to the controller 90.
A clock source 87 generates a clock signal of a specified period, and issues and supplies the clock signal to the level detector 85 or each processing unit for digital processing such as the two D/A converters 88, 89 described below.
The D/A(digital/analog) converter 88 converts the digital control signal entered from the controller 90, described below, into an analog control signal, according to the timing corresponding to the clock signal entered from the clock source 87, and issues it to the variable attenuator 82. This control signal is for controlling the amplitude change amount (that is, the amount of amplitude distortion to be generated) in the variable attenuator 82.
The D/A converter 89 converts the digital control signal entered from the controller 90, described below, into an analog control signal according to the timing corresponding to the clock signal entered from the clock source 87, and issues it to the variable phase shifter 83. This control signal is for controlling the phase change amount (that is, the amount of phase distortion to be generated) in the variable phase shifter 83.
The controller 90 is composed of, for example, a digital signal processor (DSP). On the basis of the detection result (detected level) entered from the level detector 85, the controller 90 sends a digital control signal for realizing the amplitude change amount corresponding to the detection result to the D/A converter 88 from the variable attenuator 82, and sends the digital control signal for realizing the phase change amount corresponding to the detection result to the D/A converter 89 from the variable phase shifter 83.
More specifically, in the nonlinear characteristic of the amplifier 84, since the level of the output signal is not linear to the level of the input signal (AM-AM conversion), amplitude distortion occurs, and since the phase of the output signal is not linear to the level of the input signal (AM-PM conversion), phase distortion occurs. The amount of the generated amplitude distortion or phase distortion varies depending on the level of the signal provided for the amplifier 84 (the level of the input signal, the level of the output signal). Accordingly, the controller 90 generates an amplitude distortion of the amount for canceling the amplitude distortion generated in the amplifier 84 by the variable attenuator 82, on the basis of the result of detection by the level detector 85 which is the level reflecting the level of the signal provided for the amplifier 84, and generates the phase distortion of the amount for canceling the phase distortion occurring in the amplifier 84 by the variable phase shifter 83.
For example, the correction amplitude distortion characteristic (the characteristic reverse to the amplitude distortion) for compensating for the amplitude distortion occurring in the amplifier 84 and the correction phase distortion characteristic (the characteristic reverse to the phase distortion) for compensating for the phase distortion occurring in the amplifier 84 are preliminarily calculated (or measured), and a correction table storing the control value relating to the amplitude distortion and the control value relating to the phase distortion corresponding to each other, for example, with respect to the value of detection result by the level detector 85 is saved in the memory of the controller 90. In this case, the controller 90 reads out the control value relating to the amplitude distortion and the control value relating to the phase distortion corresponding to the value of the detection result entered from the level detector 85 from the correction table, and issues these two control values to the respective D/A converters 88, 89 as a digital control signal for controlling the variable attenuator 82 and a digital control signal for controlling the variable phase shifter 83.
The controller 90 detects the level (for example, power level) of the distortion component (signal component out of the band of use) from the signal entered, for example, from the distortion extracting means 86, and can update the content of the correction table so that the level to be detected may be smaller (preferably minimum), that is, the distortion compensation amount may be larger, thereby enhancing the precision of distortion compensation.
The delay means 81 has the role of compensating for the time difference (delay time) of the timing of the one distribution signal processed by the variable attenuator 82 or variable phase shifter 83, and the timing of the control signal corresponding to the level of the other distribution signal entering the variable attenuator 82 or variable phase shifter 83 from the controller 90 through the D/A converters 88, 89 (ideally the role of matching these two timings).
That is, when generating distortion(amplitude distortion, phase distortion) by the variable attenuator 82 or variable phase shifter 83 in a certain signal portion of the input signal, the variable attenuator 82 or variable phase shifter 83 must be controlled by a control signal depending on the level of the corresponding signal portion (not other signal portion), and the delay means 81 is provided for compensating for the timing of such processing.
However, in the delay means 81 as shown in FIG. 11, for example, it is disadvantageously hard to adjust the delay time finely (precisely), and if the delay time becomes long, the precision of distortion compensation deteriorates. These defects are described in detail.
That is, in the delay means 81, it is necessary to adjust the delay time occurring in a physical wiring path, aside from the delay time taken for the processing of the D/A conversion of the digital control signal, depending on the detection result, by detecting the level of the other distribution signal.
As a result of an investigation of, for instance, an amplifying device assumed by the present inventors (however, this is an example, and the invention is not limited to this example), for adjustment of delay time, it is required to adjust in the order of 500 psec (picoseconds or 10xe2x88x9212 seconds). When this delay time is adjusted by a semi-rigid cable, a cable of about 10 cm is used. Generally, it is about 30 to 40 cm from end to end of an electronic device (circuit) board, and the distance of about 10 cm corresponds to a delay time easily occurring due to layout of wiring.
Besides, such delay time also varies depending on, for example, the parasitic capacity of the board, or individual differences of the devices. In other words, it was hitherto required to adjust the delay time by controlling the cable length for every device manufactured (for example, the amplifying device shown in FIG. 11). Moreover, this delay time varies with, for example, temperature characteristics of electronic devices, and the delay time is changed (more or less) when the temperature varies. This delay time also varies with the duration of use (aging effects).
Thus, such adjustment of delay time is a very important element in the manufacturing of the device, and it was hitherto difficult to adjust the delay time in very small time units, and if a difficult adjustment takes a very long time to perform, the device becomes very expensive.
The following example shows a result of computer simulation about the effect of the adjustment error of delay time on the distortion compensation by a predistorter.
In this example, a single carrier of 5 MHz band is used, and the condition about the waveform of the signal to be transmitted conforms to, for example, the specification of 3GPP (3rd Generation Partnership Project), that is, the number of users is 50, and the roll-off rate of the filter for limiting the band of the signal is 0.22.
Parameters for investigating the level of distortion component include third-degree mutual modulation component (IM3), fifth-degree mutual modulation component (IM5), and others, but in this example, for the sake of simplicity of explanation, the level of the distortion component is expressed by the adjacent channel power ratio (ACPR) [dBc] showing the level of power leaking to a band adjacent to the band of use.
Specifically, FIG. 15 shows an example of a result of computer simulation about the effect of the delay time (a relative delay time of a system for processing one distribution signal and a system for processing the other distribution signal) on the correction (compensation) of amplitude distortion, in which the axis of abscissas denotes the (relative) delay time [xc3x972 nsec (nanoseconds or 10xe2x88x929 seconds)] (for instance, graduation 2 indicates 4 nsec), and the axis of ordinates represents the level of distortion component expressed by the adjacent channel power ratio (ACPR) [dBc]. In this simulation, the delay time about the correction of phase distortion (for example, by variable phase shifter 83) is supposed to be zero.
Moreover, FIG. 16 shows an example of a result of computer simulation about the effect of the (relative) delay time on the correction (compensation) of phase distortion, in which the axis of abscissas denotes the (relative) delay time [xc3x972 nsec], and the axis of ordinates represents the level of distortion component expressed by the adjacent channel power ratio (ACPR) [dBc]. In this simulation, the delay time about the correction of amplitude distortion (for example, by variable phase shifter 83) is supposed to be zero.
As shown in FIG. 15, the effect of the delay time on the compensation of amplitude distortion is relatively small, but as shown in FIG. 16, the effect of delay time on compensation of phase distortion is relatively large, and the ACPR deteriorates as the delay time (or its adjustment error) becomes larger.
Herein, the reason why the effect of the delay time is greater on the compensation of phase distortion than on the compensation of amplitude distortion is that, generally, the gain variation is smaller in the amplitude distortion (AM-AM conversion) in the amplifier, but the gain variation amount is larger in the phase distortion (AM-PM conversion) in the amplifier. That is, concerning the phase distortion in the amplifier, since its variation width is large, the precision of compensation (ACPR, in this case) changes significantly if the delay time is deviated only slightly.
Numerical values presented as a result of computer simulation shown in FIG. 15 and FIG. 16 are considered to vary depending, for example, on the amplifying devices used in the simulation, but the tendency of the compensation of phase distortion having a larger effect of delay time as compared with the compensation of amplitude distortion seems to be the same as the result of this simulation.
The invention is devised to solve these conventional problems, and it is, hence, an object thereof to provide a distortion compensation apparatus capable of, realizing distortion compensation of high precision by adjusting the delay time finely (precisely), as mentioned above, and adjusting the timing for controlling the amount of distortion generated on the signal provided for the amplifier finely (precisely), when compensating for the distortion occurring in the amplifier.
To achieve the object, in the distortion compensation apparatus of the invention, distortion occurring in the amplifier is compensated for in the following manner.
That is, in the distortion generating means for generating distortion of at least one of amplitude and phase on the signal to be provided for the amplifier, the signal level detecting means detects the level of the signal provided for the amplifier, and the distortion amount control means controls the amount of distortion to be generated by the distortion generating means on the basis of the level detected by the signal level detecting means, and the control timing adjusting means adjusts the timing for controlling the amount of distortion by the distortion amount control means so that the distortion occurring in the amplifier may be compensated for sufficiently.
Therefore, by a novel method of adjustment for adjusting the timing for controlling the amount of distortion generated on the signal provided for the amplifier, for example, the timing can be adjusted finely (precisely), so that distortion compensation of a high precision is realized.
The amplifier, as the object of distortion compensation, is not particularly limited, and, for example, the amplifier may also be composed of plural amplifiers. The invention is intended to compensate for the amplitude distortion or phase distortion occurring in such an amplifier.
The degree of compensation of distortion occurring in the amplifier is preferred to be enough to decrease the distortion to zero, but in the invention, it is not always intended to decrease the distortion to zero, and it is enough to decrease the distortion substantially.
To generate distortion by the distortion generating means on the signal provided for the amplifier, for example, distortion may be generated on the signal before being amplified by the amplifier, or distortion may be also generated on the signal after being amplified by the amplifier.
The distortion generating means is preferred to have both a function of generating amplitude distortion and a function of generating phase distortion, but it may also be composed to have a function of generating amplitude distortion only or a function of generating phase distortion only.
To detect the level of the signal provided for the amplifier by the signal level detecting means, for example, the level of the signal before being amplified by the amplifier maybe detected, or the level of the signal after being amplified by the amplifier may be detected.
The level to be detected is not limited, and, for example, the level of signal amplitude or the level of signal power (usually proportional to the square of the amplitude) may be detected.
The distortion amount control means controls the amount of distortion to be generated by the distortion generating means so that the amount of distortion (distortion of reverse characteristic to the distortion occurring in the amplifier) generated by the distortion generating means is enough to cancel the amount of distortion (amplitude distortion or phase distortion) occurring in the amplifier. The amount of distortion (amplitude distortion or phase distortion) occurring in the amplifier may be estimated, for example, from the level detected by the signal level detecting means.
The degree of compensation of distortion occurring in the amplifier by the control timing adjusting means is not particularly defined, various degrees may be employed as described above, and if the distortion is not compensated to zero, it is enough, as far as the distortion compensation is realized, to be at a practically effective efficiency.
Adjustment of timing for controlling the amount of distortion by the distortion control means by the control timing adjusting means corresponds to the adjustment of delay time in the prior art.
The control timing adjusting means is preferred to adjust the timing (always or periodically) for controlling the amount of distortion by the distortion amount control means so that the amount of compensation maybe large, for example, by detecting always (or, for example, periodically) the amount of compensation of distortion occurring in the amplifier, but it may also be designed to set (or fix) the adjustment time preliminarily so that the distortion occurring in the amplifier may be compensated substantially.
In the distortion compensation apparatus of the invention, preferably, the distortion generating means is composed of circuit (an amplitude changing circuit or a phase changing circuit) for changing the amount of distortion (amplitude distortion or phase distortion) occurring depending on the analog control signal entered from outside (herein, D/A converting means as described later).
The distortion amount control means is composed of D/A converting means for converting a digital control signal into an analog control signal, and issuing it at a timing depending on a timing signal entered from outside (herein, the control timing adjusting means), and controls the amount of distortion (amplitude distortion or phase distortion) generated by the distortion generating means by sending a digital control signal to the distortion generating means through this D/A converting means.
The control timing adjusting means is composed of clock signal generating means for generating a clock signal of a predetermined period, and timing signal generating means for generating a timing signal adjusted of timing from the clock signal generated by this clock signal generating means, and adjusts the timing for controlling the amount of distortion by the distortion amount control means by sending a timing signal generated by the timing signal generating means to the D/A converting means.
In the distortion compensation apparatus of the invention, preferably, the distortion amount control means further includes memory means for storing the control value (the control value for controlling the amount of distortion (amplitude distortion or phase distortion) generated by the distortion generating means) in correspondence to the signal level, and controls the amount of distortion (amplitude distortion or phase distortion) generated by the distortion generating means by sending the control value corresponding to the level detected by the signal level detecting means to the distortion generating means through the D/A converting means as a digital control signal from the memory means.
In the distortion compensation apparatus of the invention, preferably, the timing signal generating means is composed of a variable amplifier for amplifying a clock signal generated by the clock signal generating means by a variable gain, and a limiter for limiting the level to a predetermined level and issuing the level of the signal if the level of the signal provided for the variable amplifier is more than a predetermined threshold, and adjusts the gain of the variable amplifier so that the output signal from the limiter adjusted of timing of level limiting is issued as a timing signal.
Herein, the predetermined threshold may be any one of various values depending on, for example, the status of use of the apparatus. The predetermined level is also not specified, and, for example, the predetermined threshold (its same level) may be used.
In the distortion compensation apparatus of the invention, preferably, the timing signal generating means is composed of a comparator for producing an ON signal by using a variable threshold when the level of the clock signal generated by the clock signal generating means is more than the threshold, and producing an OFF signal when the level of the clock signal is less than the threshold, and adjusts the threshold of the comparator so that the output signal from the comparator adjusted of on/off timing is issued as a timing signal.
Herein, the predetermined threshold may be any one of various values depending on, four example, the status of use of the apparatus.
For example, in the case of a digital signal composed of a value 1 and value 0, the ON signal corresponds to the value 1 signal (or value 0 signal), and the OFF signal corresponds to value 0 signal (or value 1 signal).
In the distortion compensation apparatus of the invention, preferably, the timing signal generating means is composed of a limiter for limiting the level to a predetermined level and issuing the level of the signal by using a variable threshold if the level of the clock signal generated by the clock signal generating means is more than the threshold, and adjusts the threshold of the limiter so that the output signal from the limiter adjusted of timing of level limiting is issued as a timing signal.
Herein, the predetermined threshold may be any one of various values depending on, for example, the status of use of the apparatus. The predetermined level may include various levels, and, for example, the predetermined threshold (its same level) may be used.
In the distortion compensation apparatus of the invention, preferably, the duty (the ratio of occupation of ON state in the signal composed of ON state and OFF state) of the timing signal can be varied by using a flip-flop. That is, the timing signal generating means further includes a flip-flop for receiving an output signal adjusted of timing (output signal from the limiter or comparator), and issuing a signal changed in the duty of the signal, and the output signal from the flip-flop is issued as a timing signal.
In the distortion compensation apparatus of the invention, preferably, the duty of the timing signal can be changed by using a flip-flop, and also the timing of the timing signal can be adjusted (in a wider range) by using a selector. That is, the timing signal generating means further includes a flip-flop for receiving an output signal adjusted of timing (output signal from the limiter or comparator), and issuing a signal changed in the duty of the signal and a signal inverted in on/off switching of the signal (that is, the signal changed in the duty of the output signal and inverted in on/off switching), and a selector for selecting and issuing one of the two signals produced from the flip-flop, and the output signal from the selector is issued as a timing signal.
In the distortion compensation apparatus of the invention, preferably, the distortion generating means is composed of a series connection of a variable attenuator for generating amplitude distortion to the signal by varying the amplitude of the signal provided for the amplifier, and a variable phase shifter for generating phase distortion to the signal by varying the phase of the signal provided for the amplifier.
The distortion amount control means controls the amount of amplitude distortion generated by the variable attenuator by controlling the amplitude change amount generated by the variable attenuator, and controls the amount of phase distortion generated by the variable phase shifter by controlling the phase change amount generated by the variable phase shifter.
The control timing adjusting means deviates the timing of controlling the amount of amplitude distortion generated by the distortion amount control means and the timing for controlling the amount of phase distortion generated by the distortion amount control means (for example, by the time corresponding to the deviation), depending on the lag between the timing of the signal (the signal provided for the amplifier) processed by the variable attenuator and the timing of the signal processed by the variable phase shifter.
Herein, the sequence of the connection of the means for generating amplitude distortion to the signal provided for the amplifier (herein, variable attenuator) and the means for generating phase distortion to the signal (herein, variable phase shifter) is not specified, that is, amplitude distortion may be generated first and then the phase distortion later on the signal, or phase distortion may be generated first and then the amplitude distortion later on the signal.
The distortion compensation apparatus of the invention is, preferably, installed in a wireless transmission apparatus for transmitting signals by wireless means, and compensates for the distortion occurring in the amplifier for amplifying the signal to be transmitted by the wireless transmission apparatus. The control timing adjusting means adjusts the timing for controlling the amount of distortion by the distortion amount control means, within an error in a unit of seconds of less than the value of a reciprocal number of the value of the band of the signal to be transmitted multiplied by eight (8) (for example, the value of the carrier frequency interval multiplied by the number of carriers).
The wireless transmission apparatus may be any apparatus, and preferably, the base station or repeater station (repeating amplifier) in a mobile wireless communication system may be used. The wireless transmission apparatus is not limited to the apparatus having the wireless transmission function only, and may include an apparatus having both the wireless transmission function and a wireless reception function (that is, wireless communication apparatus).
The value of eight (8) corresponds to the number of over-samplings, and the value is preferred to be 8 or more as shown above.
More specifically, the error due to timing adjustment is explained by referring to an example of computer simulation result shown in FIG. 15 and FIG. 16, as an example of digital predistortion. Ideally, an optimum distortion compensation (distortion elimination) is realized when the (relative) delay time shown in the prior art is zero, but herein, considering an actual apparatus (causing a certain error), it is investigated if effective distortion compensation is realized by decreasing the delay time by an amount by referring to the formulas and examples of computer simulation result, mentioned above.
Generally, in predistortion, distortion is generated by the envelope of the signal (the signal to be amplified) entered in the amplifier. In the amplifier, the nonlinear operation of AM-AM conversion and AM-PM conversion is carried out by the device, and it is the cause of distortion. Herein, the AM-AM conversion shows a phenomenon in which the gain of the amplifier is not constant when the level of the input signal is large, and the AM-PM conversion shows a phenomenon in which the phase (output phase) of the signal issued from the amplifier is changed depending on the level of the input signal.
Herein, the input signal is a signal to be amplified, and the band of the signal to be amplified is expressed as shown in formula (1). The carrier frequency interval is the frequency interval for detuning adjacent carriers, for example, in the multi-carrier signal (having plural carrier frequencies). For example, in the present specification of 3GPP, the carrier frequency interval is 5 MHz. The number of carriers is the number of carriers included in the multi-carrier signal (differing in frequency). For example, in the single carrier transmission, the number of carriers =1.
Band of signal to be amplified=carrier frequency intervalxc3x97number of carriersxe2x80x83xe2x80x83(1)
Assuming, for example, a multi-carrier signal of four carriers (carrier signal=1), in this case, the band width of the signal to be amplified is 20 MHz (5 MHzxc3x974 carriers).
In digital predistortion, predistortion is executed depending on the fluctuation of the envelope of the input signal. According to the generally known sampling theorem, in order to follow up the fluctuation of envelope of input signal accurately, it is required to execute sampling of 2 times or more of the signal band width.
That is, the operation period Ts [sec] of the digital circuit required in this case is expressed in formula (2). As the number of over-samplings, a numerical value of 2 or more is set.
Ts =1/(band of signal to be amplified xc3x97number of over-samplings)xe2x80x83xe2x80x83(2)
For example, in the case of a band of signal to be amplified of 5 MHz and 4-times sampling (number of over-samplings=4), Ts is 50 (=1/20 MHz) [nsec]. In this case, as over-sampling, it means to follow up (to sample) at a speed of 4 times on the envelope fluctuating at a speed of 5 MHz.
In this case, the maximum value of a relative delay error (delay time) is 25.0 nsec (half of 50 nsec). That is, in the digital system, which operates on the clock, for example, by inverting the on/off state of the clock signal in 50 nsec period composed of ON state (for example, value 1) and OFF state (for example, value 0), and selectively using the normal clock signal (non-inverted clock signal) and inverted clock signal selectively, it is possible to adjust the delay time in the unit of 25.0 nsec, that is, half value of the period.
The example of a result of computer simulation shown in FIG. 15 and FIG. 16 is discussed below. As stated above, since the AM-PM conversion is more likely to have the effect of time delay, as compared with the AM-AM conversion, it is discussed herein on the basis of the example of result of computer simulation about AM-PM conversion shown in FIG. 16.
Suppose the ACPR required in this system is, for example, xe2x88x9265 dBc (the standard is xe2x88x9260 dBc and there is a margin of 5 dB). In this case, referring to FIG. 16, the allowable relative delay error is about xe2x88x924 nsec to +2 nsec on the basis of the ideal point (the point where the relative delay time is zero). That is, the allowable fluctuation range is 6 nsec, and there is no problem as long as the delay time is less than this range.
For example, assuming a system of 4-times sampling by using a single carrier, a delay time T1 adjustable by a clock signal (of normal rotation only) is expressed in formula (3), and a delay time T2 adjustable when using also a clock signal of inverse rotation is expressed in formula (4).                                                         T1              =                              1                ⁢                                  /                                ⁢                                  (                                ⁢                signal                ⁢                                  xe2x80x83                                ⁢                band                xc3x97                number                ⁢                                  xe2x80x83                                ⁢                of                ⁢                                  xe2x80x83                                ⁢                over                ⁢                                  -                                ⁢                samplings                ⁢                                  )                                                                                                        =                              /                                  (                                      5                    ⁢                                          xe2x80x83                                        ⁢                    MHz                    xc3x97                    4                                    )                                                                                                        =                              50                ⁢                                  xe2x80x83                                ⁢                n                ⁢                                  xe2x80x83                                ⁢                sec                                                                        (        3        )                                                                    T2              =                              T1                /                2                                                                                        =                              25                ⁢                                  xe2x80x83                                ⁢                n                ⁢                                  xe2x80x83                                ⁢                sec                                                                        (        4        )            
Discussing the adjustable delay time T2 shown in formula (4), the time unit for adjusting for realizing ACPR of xe2x88x9265 dBc is within 6 nsec, and hence, it is required to adjust by the digital clock and adjust the delay time at a precision of 8 times.
Summing them up, to realize ACPR of xe2x88x9265 dBc, a time unit T3 to be adjusted is shown in formula (5). In the formula, n denotes the value of the number of over-samplings (4 in this example), and 8 is the required precision acquired by computer simulation.                                                         T3              ≦                              xe2x80x83                            ⁢                                                {                                      1                    /                                          (                                              signal                        ⁢                                                  xe2x80x83                                                ⁢                        band                        xc3x97                        n                        xc3x97                        8                                            )                                                        }                                xc3x97                                                                                                        xe2x80x83                            ⁢                              (                                  adjustment                  ⁢                                      xe2x80x83                                    ⁢                  amount                  ⁢                                      xe2x80x83                                    ⁢                  by                  ⁢                                      xe2x80x83                                    ⁢                  clock                  ⁢                                      xe2x80x83                                    ⁢                  inversion                  ⁢                                      xe2x80x83                                    ⁢                                      1                    2                                                  )                                                                                        =                              xe2x80x83                            ⁢                                                {                                      1                    /                                          (                                              5                        ⁢                                                  xe2x80x83                                                ⁢                        MHz                        xc3x97                        4                        xc3x97                        8                                            )                                                        }                                xc3x97                                  (                                      1                    2                                    )                                                                                                        =                              xe2x80x83                            ⁢                              6.25                ⁢                                  xe2x80x83                                ⁢                n                ⁢                                  xe2x80x83                                ⁢                                  sec                  /                  2                                                                                                        =                              xe2x80x83                            ⁢                              3.125                ⁢                                  xe2x80x83                                ⁢                n                ⁢                                  xe2x80x83                                ⁢                sec                                                                        (        5        )            
Suppose the ACPR required in the system is about xe2x88x9260 dBc. In this case, referring to FIG. 16, the allowable relative delay error is about xe2x88x928 nsec to +6 nsec, on the basis of the ideal point (the point where the relative delay time is zero). That is, the allowable fluctuation range is 14 nsec, so that it is enough to adjust the delay time within an error of 14 nsec.
Similarly, to realize ACPR of xe2x88x9260 dBc, a time unit T4 to be adjusted is shown in formula (6). In the formula (6), when the number of over-samplings is 4, the clock inversion is used, and further, by adjustment of delay time at a precision of 2 times, it means that the desired ACPR is achieved.                                                         T4              ≦                              xe2x80x83                            ⁢                                                {                                      1                    /                                          (                                              signal                        ⁢                                                  xe2x80x83                                                ⁢                        band                        xc3x97                        n                        xc3x97                        2                                            )                                                        }                                xc3x97                                                                                                        xe2x80x83                            ⁢                              (                                  adjustment                  ⁢                                      xe2x80x83                                    ⁢                  amount                  ⁢                                      xe2x80x83                                    ⁢                  by                  ⁢                                      xe2x80x83                                    ⁢                  clock                  ⁢                                      xe2x80x83                                    ⁢                  inversion                  ⁢                                      xe2x80x83                                    ⁢                                      1                    2                                                  )                                                                                        =                              xe2x80x83                            ⁢                                                {                                      1                    /                                          (                                              5                        ⁢                                                  xe2x80x83                                                ⁢                        MHz                        xc3x97                        4                        xc3x97                        2                                            )                                                        }                                xc3x97                                  (                                      1                    2                                    )                                                                                                        =                              xe2x80x83                            ⁢                              25                ⁢                                  xe2x80x83                                ⁢                n                ⁢                                  xe2x80x83                                ⁢                                  sec                  /                  2                                                                                                        =                              xe2x80x83                            ⁢                              12.5                ⁢                                  xe2x80x83                                ⁢                n                ⁢                                  xe2x80x83                                ⁢                sec                                                                        (        6        )            
Further, suppose that the ACPR required in the system is, for example, xe2x88x9255 dBc. Herein, ACPR=xe2x88x9255 dBc corresponds, in the 3GPP standard, to an allowable next adjacent channel leak power ratio (expressing an allowable leak power to a next adjacent channel). The next adjacent channel represents a frequency band deviated in the frequency interval from the adjacent carrier further by one carrier.
As a specific example, when the frequency of the transmission signal carrier is 2.1125 GHz and the carrier frequency interval is 5 MHz (=0.005 GHz), the frequency of the adjacent channel is 2.1175 GHz (or 2.1075 GHz), and the frequency of the next adjacent channel is 2.1225 GHz (or 2.1025 Ghz). That is, it is shifted by each carrier frequency interval (5 MHz) from the reference carrier to adjacent channel, and from adjacent channel to next adjacent channel.
Generally, in actual predistortion, a distortion situation different from the distortion occurrence situation of a pure amplifier occurs. That is, in distortion by the amplifier only, the amount of distortion attenuation attenuates as the frequency interval from the reference channel becomes wider, from reference channel to adjacent channel and to next adjacent channel. In predistortion, on the other hand, for example, the amount of distortion in the adjacent channel and the amount of distortion in the next adjacent channel may be nearly the same quantity.
Accordingly, if the leak power standard in, for example, the adjacent channel is achieved, it is not always guaranteed that the leak power standard is achieved in the next adjacent channel.
Considering this point, herein, an example of xe2x88x9255 dBc which is the standard of next adjacent channel leak power is discussed.
In this case, referring to FIG. 16, the allowable relative delay error is about xe2x88x9213 nsec to +12 nsec on the basis of the ideal point (the point where the relative delay time is zero). That is, the allowable fluctuation range is 25 nsec, and it is enough to adjust the delay time within an error of 25 nsec.
Similarly, to realize ACPR of about xe2x88x9255 dBc, a time unit T5 to be adjusted is shown in formula (7). In the formula (7), when the number of over-samplings is 4, by using the clock inversion, (by adjusting the delay time at a precision of 1 times), it is shown that the desired ACPR is achieved.                                                         T5              ≦                              xe2x80x83                            ⁢                                                {                                      1                    /                                          (                                              signal                        ⁢                                                  xe2x80x83                                                ⁢                        band                        xc3x97                        n                                            )                                                        }                                xc3x97                                                                                                        xe2x80x83                            ⁢                              (                                  adjustment                  ⁢                                      xe2x80x83                                    ⁢                  amount                  ⁢                                      xe2x80x83                                    ⁢                  by                  ⁢                                      xe2x80x83                                    ⁢                  clock                  ⁢                                      xe2x80x83                                    ⁢                  inversion                  ⁢                                      xe2x80x83                                    ⁢                                      1                    2                                                  )                                                                                        =                              xe2x80x83                            ⁢                                                {                                      1                    /                                          (                                              5                        ⁢                                                  xe2x80x83                                                ⁢                        MHz                        xc3x97                        4                        xc3x97                        8                                            )                                                        }                                xc3x97                                  (                                      1                    2                                    )                                                                                                        =                              xe2x80x83                            ⁢                              50                ⁢                                  xe2x80x83                                ⁢                n                ⁢                                  xe2x80x83                                ⁢                                  sec                  /                  2                                                                                                        =                              xe2x80x83                            ⁢                              25                ⁢                                  xe2x80x83                                ⁢                n                ⁢                                  xe2x80x83                                ⁢                sec                                                                        (        7        )            
Thus, in order to obtain the required distortion amount (herein, ACPR), it is enough to adjust the delay time at least within an error of 1/(signal band width x number of over-samplings), and further, in digital signal processing, since all operation timing is controlled by the clock, it is also possible to adjust the delay time of half clock, for example, by using the inverted clock. Further, according to the example of a computer simulation result shown in FIG. 16, preferably, a design margin for decreasing distortion to a desired distortion amount should be obtained by setting the number of over-samplings at a value of 8 or more.